Controller and access method for DDR PSRAM and operating method thereof

ABSTRACT

A controller for a DDR PSRAM is provided. The controller includes a single rate processing unit, a double rate processing unit and a selector. The signal rate processing unit obtains a single data rate data according to a first data and a first clock. The double rate processing unit obtains a double data rate data according to a second data and a second clock that is two times the frequency of the first clock. The selector selectively provides any of the single data rate data and the double data rate data to the DDR PSRAM via a common bus according to a control signal.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority of U.S. Provisional Application No.61/531,187, filed on Sep. 6, 2011, the entirety of which is incorporatedby reference herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a pseudo SRAM (PSRAM), and more particularly toa controller and a memory device of a double data rate pseudo (DDR)PSRAM, and the protocol therebetween.

2. Description of the Related Art

In portable applications, such as handheld/wireless devices, the use oflow power consuming memory is essential. A PSRAM device meets both lowpower consumption and high density requirements. A PSRAM, like aconventional dynamic random access memory (DRAM), contains dynamicmemory cells but, in terms of interface and packaging, has theappearance of a static random access memory (SRAM).

A PSRAM may operate in a burst mode. The burst mode enhances the speedof storing and retrieving data. In the burst mode, specific functionsmust occur in a predetermined sequence. Such functions are generallyperformed in response to command signals provided by a controller of thePSRAM device. The timing of the command signals is determined accordinga clock signal and is aligned to an edge (rising or falling) of theclock signal or occurs after a predetermined time after the edge (risingor falling) of the clock signal. Furthermore, in the burst mode, thePSRAM device may operate in fixed and variable modes of wait states,wherein the wait state determines a minimal number of clock cycles thatpass before a valid data is present on a data bus.

In a double data rate (DDR) SDRAM device, both the rising and fallingedges of the clock signal are trigger points for read and writeoperations. Compared with a single data rate (SDR) SDRAM device, the DDRSDRAM device using the same clock frequency will double the data rate,and a differential clock scheme is used to conform to increased timingaccuracy requirements.

BRIEF SUMMARY OF THE INVENTION

Controllers and access methods for a double data rate pseudo SRAM (DDRPSRAM) and an operating method thereof are provided. An embodiment of acontroller for a double data rate pseudo SRAM (DDR PSRAM) is provided.The controller comprises a single rate processing unit, a double rateprocessing unit and a selector. The single rate processing unit obtainsa single data rate data according to a first data and a first clock. Thedouble rate processing unit obtains a double data rate data according toa second data and a second clock that is two times the frequency of thefirst clock. The selector selectively provides any of the single datarate data and the double data rate data to the DDR PSRAM via a commonbus according to a control signal.

Furthermore, an embodiment of an access method for writing data to a DDRPSRAM is provided. A single data rate data is obtained according to afirst data and a first clock. A double data rate data is obtainedaccording to a second data and a second clock that is two times thefrequency of the first clock. Any of the single data rate data and thedouble data rate data is selectively provided to the DDR PSRAM via acommon bus.

Moreover, another embodiment of a controller for a DDR PSRAM isprovided. The controller comprises a single rate processing unit, anoutput buffer, a data strobe gating unit and a data receiver. The singlerate processing unit obtains a single data rate data according to afirst data. The output buffer provides the single data rate data to theDDR PSRAM via a common bus in a command phase. The data strobe gatingunit gates a data strobe signal from the DDR PSRAM to obtain a gateddata strobe signal in a read data phase. The data receiver receives adouble data rate data from the DDR PSRAM via the common bus according tothe gated data strobe signal, to obtain a second data.

In addition, another embodiment of an access method for reading datafrom a DDR PSRAM is provided. A single data rate data is obtainedaccording to a first data. The single data rate data is provided to theDDR PSRAM via a common bus in a command phase. A data strobe signal fromthe DDR PSRAM is gated to obtain a gated data strobe signal in a readdata phase. A double data rate data from the DDR PSRAM is received viathe common bus according to the gated data strobe signal to obtain asecond data.

Furthermore, an embodiment of an operating method performed by a doubledata rate pseudo SRAM (DDR PSRAM) is provided. A single data rate datafrom a controller is received via a common bus. A data strobe signal isprovided to the controller, and the data strobe signal is de-assertedafter a read command from the controller is accepted. A double data ratedata is transmitted to the controller via the common bus in response tothe received single data rate data. The data strobe signal is toggled inresponse to the transmitted double data rate data. The single data ratedata comprises an address of the DDR PSRAM and the double data rate datacomprises data stored in the address of the DDR PSRAM. The controller isenabled to receive the double data rate data according to the datastrobe signal.

A detailed description is given in the following embodiments withreference to the accompanying drawings.

BRIEF DESCRIPTION OF DRAWINGS

The invention can be more fully understood by reading the subsequentdetailed description and examples with references made to theaccompanying drawings, wherein:

FIG. 1 shows an electronic device comprising a controller and a DDRPSRAM;

FIG. 2 shows a waveform illustrating the signals between the controller10 and the DDR PSRAM of FIG. 1;

FIG. 3 shows an operating method for a low pin count DDR PSRAM (e.g.PSRAM of FIG. 1) according to an embodiment of the invention;

FIG. 4 shows a waveform illustrating the signals of FIG. 1 according tothe operating method of FIG. 3;

FIG. 5 shows a controller for a low pin count DDR PSRAM (e.g. PSRAM ofFIG. 1) according to an embodiment of the invention;

FIG. 6 shows a waveform illustrating the signals of the controller ofFIG. 5 according to an embodiment of the invention, wherein thecontroller performs a synchronous write operation with 4 bursts for alow pin count DDR PSRAM (e.g. PSRAM of FIG. 1); and

FIG. 7 shows a waveform illustrating the signals of the controller ofFIG. 5 according to an embodiment of the invention, wherein thecontroller performs a synchronous read operation with 4 bursts for a lowpin count DDR PSRAM (e.g. PSRAM of FIG. 1).

DETAILED DESCRIPTION OF THE INVENTION

The following description is of the best-contemplated mode of carryingout the invention. This description is made for the purpose ofillustrating the general principles of the invention and should not betaken in a limiting sense. The scope of the invention is best determinedby reference to the appended claims.

FIG. 1 shows an electronic device 100. The electronic device 100comprises a controller 10 and a DDR PSRAM 20. Furthermore, theelectronic device 100 further comprises a plurality of unidirectionaltransmission lines and a plurality of bi-directional transmission lineswith tri-state between the controller 10 and the DDR PSRAM 20. Lines 110and 120 are unidirectional transmission lines for providing a pair ofdifferential clock signals CLK and CLKn from the controller 10 to theDDR PSRAM 20. Line 130 is a unidirectional line for providing a chipselect signal CS from the controller 10 to the DDR PSRAM 20. The bus 140comprises a plurality of unidirectional transmission lines for providinga command signal CMD from the controller 10 to the DDR PSRAM 20. Theline 150 is a unidirectional line for providing a wait signal WAIT fromthe DDR PSRAM 20 to the controller 10, wherein the wait signal WAIT isused to notify the controller 10 when valid data with double data rateis present on the bus 170. Line 160 is a bi-directional transmissionline for transferring a data strobe signal DQS between the controller 10and the DDR PSRAM 20. Bus 170 is a common bus comprising a plurality ofbi-directional transmission lines for transferring of an address/datasignal AD, wherein the address/data signal AD comprising address anddata streams with different transfer rates are multiplexed into the bus170. Compared with a conventional DDR PSRAM device, the DDR PSRAM 20 isa low pin count (LPC) memory due to the sharing of the address streamsand data streams on the bus 170.

FIG. 2 shows a waveform illustrating the signals between the controller10 and the DDR PSRAM of FIG. 1. Referring to FIG. 1 and FIG. 2 together,the controller 10 de-asserts the chip select signal CS to select the DDRPSRAM 20 at time t1, and then the controller 10 provides a read commandRD_CMD to the DDR PSRAM 20 via the command signal CMD. At the same time,the controller 10 also provides an address ADDR to the DDR PSRAM 20 viathe address/data signal AD. In one embodiment, the address ADDR may bedivided into a high byte ADDR_H and a low byte ADDR_L, and thecontroller 10 provides the high byte ADDR_H via the command signal CMDand provides the low byte ADDR_L via the address/data signal AD. At timet2, the controller 10 provides the clock signals CLK and CLKn to the DDRPSRAM 20, so that the DDR PSRAM 20 can receive (may alternately refer tofetch) the command signal CMD and the address/data signal AD accordingto the clock signals CLK and CLKn in a command state. For example, inFIG. 2, the DDR PSRAM 20 receives the command signal CMD and theaddress/data signal AD in a rising edge of the clock signal CLK at timet2. When the read command RD_CMD is accepted by the DDR PSRAM 20 fromthe command signal CMD, the DDR PSRAM 20 de-asserts the wait signal WAITat time t3, to notify the controller 10 to enter a wait state. When theread command RD_CMD and the address ADDR are accepted, the DDR PSRAM 20executes a read operation to obtain the data from a memory cell of theDDR PSRAM 20 according to the address ADDR. Before transmitting theobtained data to the controller 10, the DDR PSRAM 20 asserts the waitsignal WAIT and de-asserts the data strobe signal DQS in a clock cycleCY1, which indicates that the obtained data is ready to be transmittedto the controller 10. In FIG. 2, the DDR PSRAM 20 is operating in avariable mode of the wait state, thus the time period tRL is variable inclock cycles (read latency) according to various specifications. At timet4, the DDR PSRAM 20 starts to provide the obtained data D0-D7 to thecontroller 10. Furthermore, the DDR PSRAM 20 may toggle the data strobesignal DQS in response to the data D0-D7. Thus, the controller 10 maysequentially receive the data D0-D7 according to both rising and fallingedges of the data strobe signal DQS. After the data D0-D7 are received,the controller 10 asserts the chip select signal CS at time t5 to finishthe read operation. Then, the wait signal WAIT and the data strobesignal DQS are both put into a high-impedance state in a clock cycleCY2.

In FIG. 2, the data strobe signal DQS is put into a high-impedance stateuntil the wait state is finished. Furthermore, for the data strobesignal DQS, a time period tLZ is called as a low impendence time from arising edge of the clock signal CLK in the clock cycle CY1. In general,the data strobe signal DQS is used to latch the data D0-D7, and atracking circuit is used to track the data strobe signal DQS in aconventional controller. For example, when it is detected that the waitsignal WAIT has been de-asserted (or asserted in another embodiment fromdifferent design specification), the conventional controller needs tomask the impendence period of the data strobe signal DQS, so as to gatethe data strobe signal DQS. If the masked impendence period of the datastrobe signal DQS is mistaken due to the variable time period tRL andthe time period tLZ, it is hard to obtain the valid data D0-D7 accordingto the data strobe signal DQS. For example, if the wait signal WAIT orthe data strobe signal DQS drifts in the clock cycle CY1, a transient ofthe wait signal WAIT may be later than the time period tLZ, i.e. thedata strobe signal DQS is de-asserted earlier than the transient of thewait signal WAIT, thereby generating a time violation. Therefore, it ishard to mask the impendence period of the data strobe signal DQS for theconventional controller, thus causing invalid data latching.

FIG. 3 shows an operating method for a low pin count DDR PSRAM (e.g.PSRAM 20 of FIG. 1) according to an embodiment of the invention, andFIG. 4 shows a waveform illustrating the signals of FIG. 1 according tothe operating method of FIG. 3. Referring to FIG. 3 and FIG. 4 together,in step S302, the DDR PSRAM receives a single data rate data from acontroller via a common bus coupled between the DDR PSRAM and thecontroller, wherein the single data rate data comprises an address ofthe DDR PSRAM, as shown in a command state of FIG. 4. At the same time,the DDR PSRAM also receives a read command from the controller via acommand signal. In step S304, after the read command from the controllerhas been accepted, the DDR PSRAM provides a data strobe signal DQS and await signal WAIT to the controller and de-asserts the data strobe signalDQS and the wait signal WAIT both, as shown in a wait state of FIG. 4.Next, the DDR PSRAM provides a double data rate data comprising datastored in the address of the DDR PSRAM to the controller via the commonbus (step S306), and the DDR PSRAM toggles the data strobe signal inresponse to the transmitted double data (step S308). Compared to FIG. 2,the data strobe signal of FIG. 4 is de-asserted during the wait state,as shown in label 40, thus no time period tLZ of FIG. 2 exists.Therefore, the controller receives the double data rate data accordingto the data strobe signal DQS without masking the impendence period ofthe data strobe signal DQS. In other words, the controller can directlyuse both the rising and falling edges of the data strobe signal DQS tolatch the double data rate data. Furthermore, the wait signal and thedata strobe signal are assigned to a high-impedance until the readcommand from the controller is received by the DDR PSRAM, i.e. the waitsignal and the data strobe signal are assigned to a high-impedance inthe command state. In addition, after the data D0-D7 are received by theDDR PSRAM, the controller 10 asserts the chip select signal CS to finishthe read operation, and then the wait signal WAIT and the data strobesignal DQS are both put into a high-impedance state.

FIG. 5 shows a controller 50 for a low pin count DDR PSRAM (e.g. PSRAM20 of FIG. 1) according to an embodiment of the invention. Thecontroller 50 comprises a processor 510, a clock module 530, anaddress/data module 550, a data strobe module 570 and a wait module 590.The processor 510 controls the clock module 530 to provide thedifferential clock signals CLK and CLKn to the DDR PSRAM. The clockmodule 530 comprises a clock generator 532 and two output buffers 534and 536, wherein the clock generator 532 comprises a frequency divider538. The clock generator 532 generates the clock signals CLK1X and CLK2Xaccording to an input clock CLKin, wherein the clock signal CLK2X is twotimes the frequency of the clock signal CLK1X. In one embodiment, theinput clock CLKin is provided by an oscillator. Furthermore, thefrequency divider 538 divides the clock signal CLK2X to generate theCLK1X clock signal. The differential clock signals CLK and CLKn aregenerated from the CLK1X clock signal, and has the same frequency asthat of the CLK1X clock signal. Moreover, the differential clock signalsCLK and CLKn are provided to the DDR PSRAM via the output buffers 536and 534, respectively. The processor 510 controls the address/datamodule 550 to provide address streams to the DDR PSRAM in a commandphase, provide data streams to the DDR PSRAM in a write data phase, andreceive data streams from the DDR PSRAM in a read data phase. Theaddress/data module 550 comprises an output control unit 552, an outputbuffer 554, an input buffer 556, a single rate processing unit 558, adouble rate processing unit 560, a selector 562, a data receiver 564 anda storage unit 566. The selector 562 is used to selectively provide anyof the output of the single rate processing unit 558 and the double rateprocessing unit 560 to the output buffer 554 according to a controlsignal WDATA_PHASE_EN. In the embodiment, the selector 562 is amultiplexer (MUX). The processor 510 controls the data strobe module 570to provide a data strobe signal to the DDR PSRAM in the write data phaseand receive a data strobe signal from the DDR PSRAM in the read dataphase. The data strobe module 570 comprises an input buffer 572, anoutput buffer 574, a data strobe gating unit 576, a data strobegenerating unit 578 and an output control unit 580. The processor 510controls the wait module 590 to receive a wait signal from the DDR PSRAMin the read data phase. The wait module 590 comprises an input buffer592, a synchronization unit 594 and a read control unit 596. Details ofdescriptions illustrating the operations of the address/data module 550,the data strobe module 570 and the wait module 590 are described below.

FIG. 6 shows a waveform illustrating the signals of the controller 50 ofFIG. 5 according to an embodiment of the invention, wherein thecontroller 50 performs a synchronous write operation with 4 bursts for alow pin count DDR PSRAM (e.g. PSRAM 20 of FIG. 1). Referring to FIG. 5and FIG. 6 together, during a time period TP1, the processor 510provides an enable signal CMD_EN with a logic level HIGH to the outputcontrol unit 552, so as to control the output control unit 552 to enablethe output buffer 554. At the same time, the processor 510 also providesa signal ADDRO with address information ADDR to the single rateprocessing unit 558. Next, the single rate processing unit 558 obtains asingle data rate data with the address information ADDR according to theclock signal CLK1X and provides the single data rate data to theselector 562. Furthermore, the processor 510 provides a control signalWDATA_PHASE_EN with a logic level LOW to the selector 562, so as tocontrol the selector 562 to output the single data rate data provided bythe single rate processing unit 558, to the output buffer 554. Thus, anaddress/data signal AD with address information ADDR is provided to theDDR PSRAM in a command phase. In the meantime, a command signal CMD witha write command WR_CMD is sent to the DDR PSRAM via a command bus (e.g.140 of FIG. 1). Next, from a time period TP2 to a time period TP5, theprocessor 510 provides the control signal WDATA_PHASE_EN with a logiclevel HIGH to the output control units 552 and 580, so as to control theoutput control units 552 and 580 to enable the output buffers 554 and574. According to fixed write latency (such as N cycles), the processor510 provides the control signal WDATA_PHASE_EN with a logic level HIGHupon the N clock cycle of the clock signal CLK1X after sending the writecommand, so as to enter the write data phase. Furthermore, the processor510 provides the control signal WDATA_PHASE_EN to the selector 562, soas to provide an output of the double rate processing unit 560 to theoutput buffer 554. The processor 510 provides the signal WDATAO_L with adata D0 and the signal WDATAO_H with a data D1 to the double rateprocessing unit 560 during the time period TP3, and the processor 510provides the signal WDATAO_L with a data D2 and the signal WDATAO_H witha data D3 to the double rate processing unit 560 during the time periodTP4. The double rate processing unit 560 provides a double data ratedata with the data D0, D1, D2 and D3 to the output buffer 554 via theselector 562 according to the clock signal CLK2X. Thus, an address/datasignal AD with the data D0, D1, D2 and D3 is provided to the DDR PSRAMin the write data phase. In the embodiment, the double rate processingunit 560 alternately provides the data of the signals WDATAO_L andWDATAO_H as the double data rate data according to the clock signalCLK2X. Therefore, the address/data signal AD with data streams formed bythe data D0-D3 can be transmitted to the DDR PSRAM in sequence.Moreover, during the time periods TP3 and TP4, the processor 510provides an enable signal DQSEN with a logic level HIGH to the datastrobe generating unit 578, so as to control the data strobe generatingunit 578 to provide a data strobe signal DQS to the DDR PSRAM via theoutput buffer 574. Thus, the DDR PSRAM can receive the address/datasignal AD according to both rising and falling edges of the data strobesignal DQS, and then the DDR PSRAM writes the data D0, D1, D2 and D3into memory cells thereof according to the address information ADDR.

FIG. 7 shows a waveform illustrating the signals of the controller 50 ofFIG. 5 according to an embodiment of the invention, wherein thecontroller 50 performs a synchronous read operation with 4 bursts for alow pin count DDR PSRAM (e.g. PSRAM 20 of FIG. 1). Referring to FIG. 5and FIG. 7 together, during a time period TP6, the processor 510provides an enable signal CMD_EN with a logic level HIGH to the outputcontrol unit 552, so as to control the output control unit 552 to enablethe output buffer 554. At the same time, the processor 510 also providesa signal ADDRO with address information ADDR to the single rateprocessing unit 558. Next, the single rate processing unit 558 obtains asingle data rate data with the address information ADDR according to theclock signal CLK1X and provides the single data rate data to theselector 562. Furthermore, the processor 510 provides a control signalWDATA_PHASE_EN with a logic level LOW to the selector 562, so as tocontrol the selector 562 to output the single data rate data provided bythe single rate processing unit 558, to the output buffer 554. Thus, anaddress/data signal AD with address information ADDR is provided to theDDR PSRAM in a command phase. In the meantime, a command signal CMD witha read command RD_CMD is sent to the DDR PSRAM via a command bus (e.g.140 of FIG. 1). As described in the operating method of FIG. 3, afterthe read command RD_CMD of the command signal CMD from the controller isaccepted, the DDR PSRAM provides a data strobe signal DQS and a waitsignal WAIT to the controller and de-asserts the data strobe signal andthe wait signal both in a wait state. In the wait module 590, the inputbuffer 592 transmits the wait signal WAIT from the DDR PSRAM to thesynchronization unit 594 for synchronization, and the synchronizationunit 594 provides a synchronized wait signal to the read control unit596. Furthermore, the processor 510 provides the enable signalRDATA_PHASE_EN with a logic level HIGH upon 2 clock cycles after sendingthe read command RD_CMD, so as to enter a read data phase. Furthermore,the read control unit 596 provides a ready signal RDATA_PTR_GEN to thestorage unit 566. In a read data phase, the data strobe gating unit 576is enabled by the enable signal RDATA_PHASE_EN, to gate the data strobesignal DQS toggled by the DDR PSRAM, so as to obtain a gated signalDQS_CG and provide the gated signal DQS_CG to the read receiver 564. Theread receiver 564 receives the address/data signal AD from the DDR PSRAMand stores the data of the address/data signal AD into first in firstout units (FIFOs) of the storage unit 566 according to the gated signalDQS_CG, wherein the address/data signal AD comprises data streams formedby the data units D0, D1, D2 and D3 that are stored in the memory cellsof the DDR PSRAM corresponding to the address information ADDR. Forexample, a first rising edge of the gated signal DQS_CG is used to latchthe data D0 into the FIFO FIFOR[0], a first falling edge of the gatedsignal DQS_CG is used to latch the data D1 into the FIFO FIFOF[0], asecond rising edge of the gated signal DQS_CG is used to latch the dataD2 into the FIFO FIFOR[1], and a second falling edge of the gated signalDQS_CG is used to latch the data D3 into the FIFO FIFOF[1]. In otherembodiments, the storage unit 566 may comprises the register or otherstorage cells to store the data of the address/data signal AD.Furthermore, the storage unit 566 provides the data units stored in theFIFOR[1:0] and FIFOF[1:0] to the processor 510 via the signalsRDATA_IN_R and RDATA_IN_L according to the ready signal RDATA_PTR_GEN.Thus, the processor 510 obtains the data D0, D1, D2 and D3 correspondingto the address information ADDR. After the data D0, D1, D2 and D3 arestored by the processor 510, the processor 510 de-asserts the enablesignal RDATA_PHASE_EN, to finish the read data phase.

While the invention has been described by way of example and in terms ofthe preferred embodiments, it is to be understood that the invention isnot limited to the disclosed embodiments. To the contrary, it isintended to cover various modifications and similar arrangements (aswould be apparent to those skilled in the art). Therefore, the scope ofthe appended claims should be accorded the broadest interpretation so asto encompass all such modifications and similar arrangements.

What is claimed is:
 1. A controller for a double data rate pseudo SRAM(DDR PSRAM), comprising: a single rate processing unit, obtaining asingle data rate data according to a first data and a first clock; adouble rate processing unit, obtaining a double data rate data accordingto a second data and a second clock that is two times the frequency ofthe first clock; and a selector, selectively providing any of the singledata rate data and the double data rate data to the DDR PSRAM via acommon bus according to a control signal.
 2. The controller as claimedin claim 1, wherein the control signal controls the selector to providethe single data rate data to the DDR PSRAM in a command phase, and thecontrol signal controls the selector to provide the double data ratedata to the DDR PSRAM in a write data phase.
 3. The controller asclaimed in claim 1, wherein the first data comprises an address of theDDR PSRAM and the second data comprises data to be written into theaddress of the DDR PSRAM.
 4. The controller as claimed in claim 1,further comprising: a frequency divider, dividing the second clock toobtain a third clock and providing the third clock to the DDR PSRAM,wherein the first clock and the third clock have the same frequency,wherein the DDR PSRAM receives the single data rate data according tothe third clock.
 5. The controller as claimed in claim 1, furthercomprising: a data strobe generating unit, providing a data strobesignal to the DDR PSRAM according to the second clock when the doubledata rate data is provided to the DDR PSRAM by the selector, wherein theDDR PSRAM receives the double data rate data according to the datastrobe signal.
 6. The controller as claimed in claim 5, wherein thesecond data comprises a plurality of data units that are divided into afirst group and a second group, and the double rate processing unitalternately provides the data units of the first and second groups asthe double data rate data according to the second clock, therebyenabling the DDR PSRAM to receive the data units of the first group inresponse to a rising edge of the data strobe signal and receive the dataunits of the second group in response to a falling edge of the datastrobe signal.
 7. An access method for writing data to a double datarate pseudo SRAM (DDR PSRAM), comprising: obtaining a single data ratedata according to a first data and a first clock; obtaining a doubledata rate data according to a second data and a second clock that is twotimes the frequency of the first clock; and selectively providing any ofthe single data rate data and the double data rate data to the DDR PSRAMvia a common bus.
 8. The access method as claimed in claim 7, whereinthe step of selectively providing the single data rate data or thedouble data rate data to the DDR PSRAM via the common bus furthercomprises: providing the single data rate data to the DDR PSRAM in acommand phase; and providing the double data rate data to the DDR PSRAMin a write data phase.
 9. The access method as claimed in claim 7,wherein the first data comprises an address of the DDR PSRAM and thesecond data comprises data to be written into the address of the DDRPSRAM.
 10. The access method as claimed in claim 7, further comprising:dividing the second clock to obtain a third clock and providing thethird clock to the DDR PSRAM, wherein the first clock and the thirdclock have the same frequency, wherein the DDR PSRAM receives the singledata rate data according to the third clock.
 11. The access method asclaimed in claim 7, further comprising: providing a data strobe signalto the DDR PSRAM according to the second clock when the double data ratedata is provided to the DDR PSRAM, wherein the DDR PSRAM receives thedouble data rate data according to the data strobe signal.
 12. Theaccess method as claimed in claim 11, wherein the second data comprisesa plurality of data units that are divided into a first group and asecond group, and the step of obtaining the double data rate dataaccording to the second data and the second clock further comprises:alternately providing the data units of the first and second groups asthe double data rate data according to the second clock, therebyenabling the DDR PSRAM to receive the data units of the first group inresponse to a rising edge of the data strobe signal and receive the dataunits of the second group in response to a falling edge of the datastrobe signal.
 13. A controller for a double data rate pseudo SRAM (DDRPSRAM), comprising: a single rate processing unit, obtaining a singledata rate data according to a first data; an output buffer, providingthe single data rate data to the DDR PSRAM via a common bus in a commandphase; a data strobe gating unit, gating a data strobe signal from theDDR PSRAM to obtain a gated data strobe signal in a read data phase; anda data receiver, receiving a double data rate data from the DDR PSRAMvia the common bus according to the gated data strobe signal, to obtaina second data.
 14. The controller as claimed in claim 13, wherein thefirst data comprises an address of the DDR PSRAM and the second datacomprises data stored in the address of the DDR PSRAM.
 15. Thecontroller as claimed in claim 13, further comprising: a clockgenerator, providing a clock signal to the DDR PSRAM thereby enablingthe DDR PSRAM to receive the single data rate data according to theclock signal.
 16. The controller as claimed in claim 13, wherein thesecond data comprises a plurality of data units that are divided into afirst group and a second group, and the data receiver provides the dataunits of the first group to a first FIFO in response to a rising edge ofthe gated data strobe signal and provides the data units of the secondgroup to a second FIFO in response to a falling edge of the gated datastrobe signal.
 17. The controller as claimed in claim 16, furthercomprising: a processor, providing the first data; a synchronizationunit, synchronizing a wait signal from the DDR PSRAM, wherein the waitsignal is de-asserted during a wait state; and a read control unit,obtaining a ready signal according to the synchronized wait signal,wherein the first FIFO and the second FIFO output the data units of thefirst group and the second group to the processor according to the readysignal.
 18. An access method for reading data from a double data ratepseudo SRAM (DDR PSRAM), comprising: obtaining a single data rate dataaccording to a first data; providing the single data rate data to theDDR PSRAM via a common bus in a command phase; gating a data strobesignal from the DDR PSRAM to obtain a gated data strobe signal in a readdata phase; and receiving a double data rate data from the DDR PSRAM viathe common bus according to the gated data strobe signal to obtain asecond data.
 19. The access method as claimed in claim 18, wherein thefirst data comprises an address of the DDR PSRAM and the second datacomprises data stored in the address of the DDR PSRAM.
 20. The accessmethod as claimed in claim 18, further comprising: providing a clocksignal to the DDR PSRAM, thereby enabling the DDR PSRAM to receive thesingle data rate data according to the clock signal.
 21. The accessmethod as claimed in claim 18, wherein the second data comprises aplurality of data units that are divided into a first group and a secondgroup, and the step of the receiving the double data rate data from theDDR PSRAM via the common bus according to the gated data strobe signalto obtain the second data further comprises: providing the data units ofthe first group to a first FIFO in response to a rising edge of thegated data strobe signal; and providing the data units of the secondgroup to a second FIFO in response to a falling edge of the gated datastrobe signal.
 22. The access method as claimed in claim 18, furthercomprising: synchronizing a wait signal from the DDR PSRAM, wherein thewait signal is de-asserted during a wait state; obtaining a ready signalaccording to the synchronized wait signal; and outputting the data unitsof the first group and the second group to a processor by the first andsecond FIFOs according to the ready signal.
 23. An operating methodperformed by a double data rate pseudo SRAM (DDR PSRAM), comprising:receiving a single data rate data from a controller via a common bus;providing a data strobe signal to the controller, and de-asserting thedata strobe signal after a read command from the controller is accepted;transmitting a double data rate data to the controller via the commonbus in response to the received single data rate data; and toggling thedata strobe signal in response to the transmitted double data rate data,wherein the single data rate data comprises an address of the DDR PSRAMand the double data rate data comprises data stored in the address ofthe DDR PSRAM, thereby enabling the controller to receive the doubledata rate data according to the data strobe signal.
 24. The operatingmethod as claimed in claim 23, further comprising: providing a waitsignal to the controller, and de-asserting the wait signal after theread command from the controller has been accepted; and asserting thewait signal when the double data rate data corresponding to the readcommand is ready to be transmitted.
 25. The operating method as claimedin claim 23, wherein the wait signal and the data strobe signal areassigned to a high-impedance until the read command from the controlleris received.
 26. The operating method as claimed in claim 23, furthercomprising: receiving a command signal from the controller; receiving aclock signal from the controller; and obtaining the single data ratedata and the read command of the command signal according to the clocksignal.